ADZS-21469-EZLITE【PDF 8/62 页】KIT EVAL EZ LITE ADSP-21469

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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469

Table 4. ADSP-21462W/ADSP-21469/ADSP-21469W Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Preliminary Technical Data

Long Word (64 bits)

BLOCK 0 RAM

0x0004 9000–0x0004 EFFF

Reserved

0x0004 F000–0x0005 8FFF

BLOCK 1 RAM

0x0005 9000–0x0005 EFFF

Reserved

0x0005 F000–0x0005 FFFF

BLOCK 2 RAM

0x0006 0000–0x0006 3FFF

Reserved

0x0006 4000–0x0006 FFFF

BLOCK 3 RAM

0x0007 0000–0x0007 3FFF

Reserved

0x0007 4000–0x0007 FFFF

Instruction Word (48 bits)

BLOCK 0 RAM

0x0008 C000-0x0009 3FFF

Reserved

0x0009 E000–0x000B 1FFF

BLOCK 1 RAM

0x000A C000-0x000B 3FFF

Reserved

0x000B E000–0x000B FFFF

BLOCK 2 RAM

0x000C 0000–0x000C 5554

Reserved

0x000C 8000–0x000D FFFF

BLOCK 3 RAM

0x000E 0000–0x000E 5554

Reserved

0x000E 8000–0x000F FFFF

Normal Word (32 bits)

BLOCK 0 RAM

0x0009 2000-0x0009 DFFF

Reserved

0x0009 E000–0x000B 1FFF

BLOCK 1 RAM

0x000B 2000-0x000B DFFF

Reserved

0x000B E000–0x000B FFFF

BLOCK 2 RAM

0x000C 0000-0x000C 7FFF

Reserved

0x000C 8000–0x000D FFFF

BLOCK 3 RAM

0x000E 0000–0x000E 7FFF

Reserved

0x000E 8000–0x000F FFFF

Short Word (16 bits)

BLOCK 0 RAM

0x0012 4000–0x0013 BFFF

Reserved

0x0013 C000–0x0016 3FFF

BLOCK 1 RAM

0x0016 4000-0x0017 BFFF

Reserved

0x0017 C000–0x0017 FFFF

BLOCK 2 RAM

0x0018 0000–0x0018 FFFF

Reserved

0x0019 0000–0x001B FFFF

BLOCK 3 RAM

0x001C 0000–0x001C FFFF

Reserved

0x001D 0000–0x001F FFFF

DDR2 Support

Table 6. External Memory for DDR2 DRAM Addresses

The ADSP-2146x supports a 16-bit DDR2 interface operating at

a maximum frequency of half the core clock. Execution from

external memory is supported. External memory devices up to 2

Gbits in size can be supported. Delay line DMA functionality

supported.

DDR2 DRAM Controller

The DDR2 DRAM controller provides an 16-bit interface to up

to four separate banks of industry-standard DDR2 DRAM

Bank

Bank 0

Bank 1

Bank 2

Bank 3

Size in

Words

62M

64M

64M

64M

Address Range

0x0020 0000 – 0x03FF FFFF

0x0400 0000 – 0x07FF FFFF

0x0800 0000 – 0x0BFF FFFF

0x0C00 0000 – 0x0FFF FFFF

devices. Fully compliant with the DDR2 DRAM standard, each

bank can has its own memory select line (DDR2_CS3-

DDR2_CS0), and can be configured to contain between 32M

bytes and 256M bytes of memory. DDR2 DRAM external mem-

ory address space is shown in Table 6

A set of programmable timing parameters is available to config-

ure the DDR2 DRAM banks to support memory devices.

Table 5. External Memory for Non DDR2 DRAM Addresses

Size in

Note that the external memory bank addresses shown are for

normal-word (32-bit) accesses. If 48-bit instructions as well as

32-bit data are both placed in the same external memory bank,

care must be taken while mapping them to avoid overlap. In

case of 32-bit wide external memory, two 48-bit instructions

will be stored in three 32-bit wide memory locations. For exam-

ple, if 2k instructions are placed in 32-bit wide external memory

starting at the bank 0 normal-word base address 0x0030 0000

(corresponding to instruction address 0x0020 0000) and ending

at address 0x0030 0BFF (corresponding to instruction address

0x0020 07FF), then data buffers can be placed starting at an

Bank

Bank 0

Bank 1

Bank 2

Bank 3

Words

14M

16M

16M

16M

Address Range

0x0020 0000 – 0x00FF FFFF

0x0400 0000 – 0x04FF FFFF

0x0800 0000 – 0x08FF FFFF

0x0C00 0000 – 0x0CFF FFFF

address that is offset by 3k 32-bit words (for example, starting at

0x0030 0C00).

Asynchronous Memory Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, flash, and EPROM, as well

as I/O devices that interface with standard memory control

Rev. PrC

| Page 8 of 62 | January 2009

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